Skip to main navigation Skip to search Skip to main content

Towards reliability and performance-aware Wireless Network-on-Chip design

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

8 Citations (Scopus)

Abstract

Recently Hybrid Wired-Wireless Network-on-Chip (WiNoC) has emerged to solve the poor scalability and performance issues of modern System-on-Chip (SoC) design. However, conventional on-chip wireless interconnect has a high error rates which have drastic effects on the total reliability of the WiNoC. In this paper, we propose an improved wireless interconnect fabric that is able to achieve a similar error rate as traditional wireline channels as an effort to improve the overall reliability of WiNoCs. A novel transducer is designed to launch surface wave signals into a commercially available thin metal conductor coated with a low cost dielectric material to generate wireless signals with high signal strength. Experimental results show that, for a 60GHz center frequency, the proposed communication fabric can achieve an operational bandwidth of about 60GHz. Compared to existing WiNoCs, the proposed communication fabric can improve the reliability of WiNoCs with average gains of 21.4%, 13.8% and 10.7% performance efficiencies in terms of maximum sustainable load, throughput and delay, respectively.

Original languageEnglish
Title of host publicationProceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2015
Pages205-210
Number of pages6
ISBN (Electronic)9781509003129
DOIs
Publication statusPublished - 2 Nov 2015
Externally publishedYes
Event28th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2015 - Amherst, United States
Duration: 12 Oct 2015 → 14 Oct 2015

Publication series

NameProceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2015

Conference

Conference28th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2015
Country/TerritoryUnited States
CityAmherst
Period12/10/15 → 14/10/15

Fingerprint

Dive into the research topics of 'Towards reliability and performance-aware Wireless Network-on-Chip design'. Together they form a unique fingerprint.

Cite this