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On the design of a self-reconfigurable SoPC based cryptographic engine

Research output: Contribution to conference › Paper › peer-review

8 Citations (Scopus)

Abstract

This paper presents a SoPC (System-on-a-Programmable-Chip) embedded system featuring self-reconfigurable capability. It addresses the factors that limit the system performance when FPGAs are used to implement various encryption algorithms dynamically. The limiting factors are the data transfer rate between the host and the FPGA, and the reconfiguration latency. The results generated by the cryptographic engine reported in this paper show that in order to attain optimal performance, it is crucial to floor-plan the reconfigurable part of the FPGA.

Original languageEnglish
Pages876-881
Number of pages6
Publication statusPublished - 2004
Externally publishedYes
EventProceedings - 24th International Conference on Distributed Computing Systems Workshops - Hachioji, Japan
Duration: 23 Mar 2004 → 24 Mar 2004

Conference

ConferenceProceedings - 24th International Conference on Distributed Computing Systems Workshops
Country/TerritoryJapan
CityHachioji
Period23/03/04 → 24/03/04

Keywords

  • Dynamic reconfiguration
  • Embedded system
  • Encryption engine
  • FPGA
  • ICAP
  • SoPC

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