Abstract
This paper presents a SoPC (System-on-a-Programmable-Chip) embedded system featuring self-reconfigurable capability. It addresses the factors that limit the system performance when FPGAs are used to implement various encryption algorithms dynamically. The limiting factors are the data transfer rate between the host and the FPGA, and the reconfiguration latency. The results generated by the cryptographic engine reported in this paper show that in order to attain optimal performance, it is crucial to floor-plan the reconfigurable part of the FPGA.
| Original language | English |
|---|---|
| Pages | 876-881 |
| Number of pages | 6 |
| Publication status | Published - 2004 |
| Externally published | Yes |
| Event | Proceedings - 24th International Conference on Distributed Computing Systems Workshops - Hachioji, Japan Duration: 23 Mar 2004 → 24 Mar 2004 |
Conference
| Conference | Proceedings - 24th International Conference on Distributed Computing Systems Workshops |
|---|---|
| Country/Territory | Japan |
| City | Hachioji |
| Period | 23/03/04 → 24/03/04 |
Keywords
- Dynamic reconfiguration
- Embedded system
- Encryption engine
- FPGA
- ICAP
- SoPC
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