On IIR-based bit-stream multipliers

We analyze the existing bi-level IIR-based bit-stream multiplier and propose selection criteria for the key design parameter governing droop and phase linearity. Based on the proposed choice of parameter, we then extend the bi-level design to tri- and quad-level architectures that offer better signal-to-noise performance. Hardware complexity and noise performance of these designs are also contrasted with previously proposed FIR-based bit-stream multipliers. Useful design guidelines are subsequently drawn.