Hardware task scheduling for an fpga-based mobile robot in wireless sensor networks

Introduction The regular structure of field programmable gate arrays (FPGAs) enables the utilization of massively parallel circuit design for hardware acceleration of software tasks. Specifically, we can offload some computation-intensive tasks in software applications, which are originally executed in the instruction set processor, to FPGAs so as to increase the overall system efficiency. Specifically, an FPGA-based system offers the following advantages over a traditional processor-based system: Computation efficiency: FPGAs, a kind of (re)programmable chips, have traditionally been used for hardware prototyping or as glue logic for connecting different components in a system. With today’s advanced chip technology, FPGAs’ gates are clocked at high rate and of high density and have abundant dedicated hardware resources, which brings about an amazing computer architecture for high performance computing-reconfigurable computing. FPGAs can typically achieve 20-100 speedup factors over processors.