Bit-stream adders and multipliers for tri-level sigma-delta modulators

Chiu Wa Ng; Ngai Wong; Tung Sang Ng

doi:10.1109/TCSII.2007.906173

Bit-stream adders and multipliers for tri-level sigma-delta modulators

Chiu Wa Ng
, Ngai Wong
, Tung Sang Ng

Research output: Contribution to journal › Article › peer-review

18 Citations (Scopus)

Abstract

We propose both adder and multiplier circuits for bit-stream signal processing customized for tri-level sigma-delta modulated signals. These architectures are the 2-bit extensions from the existing 1-bit bit-stream adders and multipliers, and are shown to offer better signal-to-noise performance. Field-programmable gate array implementations then confirm their efficacy.

Original language	English
Pages (from-to)	1082-1086
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	54
Issue number	12
DOIs	https://doi.org/10.1109/TCSII.2007.906173
Publication status	Published - 2007
Externally published	Yes

Keywords

Adder circuit
Multiplier circuit
Oversampling
Tri-level sigma-delta modulation

Access to Document

10.1109/TCSII.2007.906173

Cite this

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title = "Bit-stream adders and multipliers for tri-level sigma-delta modulators",

abstract = "We propose both adder and multiplier circuits for bit-stream signal processing customized for tri-level sigma-delta modulated signals. These architectures are the 2-bit extensions from the existing 1-bit bit-stream adders and multipliers, and are shown to offer better signal-to-noise performance. Field-programmable gate array implementations then confirm their efficacy.",

keywords = "Adder circuit, Multiplier circuit, Oversampling, Tri-level sigma-delta modulation",

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year = "2007",

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T1 - Bit-stream adders and multipliers for tri-level sigma-delta modulators

AU - Ng, Chiu Wa

AU - Wong, Ngai

AU - Ng, Tung Sang

PY - 2007

Y1 - 2007

N2 - We propose both adder and multiplier circuits for bit-stream signal processing customized for tri-level sigma-delta modulated signals. These architectures are the 2-bit extensions from the existing 1-bit bit-stream adders and multipliers, and are shown to offer better signal-to-noise performance. Field-programmable gate array implementations then confirm their efficacy.

AB - We propose both adder and multiplier circuits for bit-stream signal processing customized for tri-level sigma-delta modulated signals. These architectures are the 2-bit extensions from the existing 1-bit bit-stream adders and multipliers, and are shown to offer better signal-to-noise performance. Field-programmable gate array implementations then confirm their efficacy.

KW - Adder circuit

KW - Multiplier circuit

KW - Oversampling

KW - Tri-level sigma-delta modulation

UR - https://www.scopus.com/pages/publications/44649136353

U2 - 10.1109/TCSII.2007.906173

DO - 10.1109/TCSII.2007.906173

M3 - Article

AN - SCOPUS:44649136353

SN - 1549-7747

VL - 54

SP - 1082

EP - 1086

JO - IEEE Transactions on Circuits and Systems II: Express Briefs

JF - IEEE Transactions on Circuits and Systems II: Express Briefs

IS - 12

ER -

Bit-stream adders and multipliers for tri-level sigma-delta modulators

Abstract

Keywords

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