A 10T SRAM-Based PUF Enhanced by In-Memory Computing for Secure Authentication

Consumer electronics face growing security threats, necessitating robust hardware-level protection. Physically Un-clonable Functions (PUFs) offer a promising solution by lever-aging intrinsic device variations for secure identification and authentication. Compute in memory has proven to be an effective architecture for doing DNN inference at the edge by reducing memory-processor communication. However, security issues such as model leaking are rarely addressed in mainstream research. To enable reliable deployment in resource-constrained environments, there is an urgent need for CIM designs that incorporate security without sacrificing performance. Using the inherent characteristics of 10T SRAM cells and the bitline discharge technique, this paper explores a secure and reliable in-memory computing architecture to implement PUF directly within memory arrays. The major goal of this work is to create and evaluate a comprehensive 10T SRAM-based framework that can handle secure key generation based on PUF with little overhead. A single 10T SRAM cell is designed and characterized at the start of the study, which shows write power is 2.9% lower and better delay 14.6 % faster then convetional 6T-SRAM cell then moves on to a 64x32 array layout with area 1905(μ m²). Post layout simulation is focused in the design with the delay 842.36ns and static power 1.18 mW. The inter chip-HD 0.49% is calculated with PUF energy 85 fJ/bit. Security measures that are portable, energy-efficient, and attack-resistant are desperately needed given the explosive growth of Edge Artificial Intelligence (Edge AI) systems.